Unlike conventional random access memory (RAM) chip technologies, in magnetic RAM (MRAM) data is not stored as electric charge, but is instead stored by magnetic polarization of storage elements. The elements are formed from two magnetically polarized plates, each of which can maintain a magnetic polarization field, separated by a thin insulating layer, which together form a magnetic tunnel junction (MTJ). One of the two plates is a permanent magnet (hereinafter “fixed layer”) set to a particular polarity; the polarization of the other plate (hereinafter “free magnetization layer” or “free layer”) will change to match that of a sufficiently strong external field. A memory device may be built from a grid of such cells.
Reading the polarization state of an MRAM cell is accomplished by measuring the electrical resistance of the cell's MTJ. A particular cell is conventionally selected by powering an associated transistor that switches current from a supply line through the MTJ to a ground. Due to the tunneling magnetoresistance effect, the electrical resistance of the cell changes due to the relative orientation of the polarizations in the two magnetic layers of the MTJ. By measuring the resulting current, the resistance inside any particular cell can be determined, and from this the polarity of the free writable layer determined. If the two layers have the same polarization, this is considered to mean State “0”, and the resistance is “low,” while if the two layers are of opposite polarization the resistance will be higher and this means State “1”.
Data is written to the cells using a variety of techniques. In conventional MRAM, an external magnetic field is provided by current in a wire in proximity to the cell, which is strong enough to align the free layer. Spin-transfer-torque (STT) MRAM uses spin-aligned (“polarized”) electrons to directly torque the domains of the free layer. Specifically, such polarized electrons flowing into the free layer by exerting a sufficient torque to realign (e.g., reverse) the magnetization of the free layer
One significant determinant of a memory system's cost is the density of the components. Smaller components, and fewer components for each cell, enable more cells to be packed onto a single chip, which in turn means more chips can be produced at once from a single semiconductor wafer and fabricated at lower cost and improved yield. Scaling integrated circuits to higher device pitch density, however, increases the demands on the critical dimensions of mask registration in fabricating the multiple layers of such devices.
In addition, the manufacturing process flow impacts cost. The conventional processes to fabricate MRAM are complex, requiring a number of masks dedicated solely to the fabrication of the magnetic tunnel junction (MTJ) structure. There is a need, therefore, for improved methods for MRAM fabrication, especially if the fabrication processes could be integrated into the conventional semiconductor BEOL (back-end-of-line) process flow with relaxed mask registration requirements.